1. Field of the Invention
The present invention relates to the technical field of cryptography and, in particular, the present invention relates to the technical sub-field of cryptographic bus encryption.
2. Description of Related Art
In order to transfer data from one device to another device on a semiconductor board, signal busses having several parallel lines are frequently used. However, to avoid signal tapping on these bus lines in security-relevant applications, bus encryption is frequently employed so that the data are transferred between the two devices only in an encrypted form. To obtain the information exchanged between the two devices, a potential attacker would have to know the respective encryption key or a pertaining decryption key. Often, a stream cipher is used in the conventional art for this bus encryption.
Such a data transfer by means of bus encryption is illustrated in greater detail in a block circuit diagram in FIG. 2. Here, the (encrypted) data mt are transferred between a first device CPU and a second device AES by means of a first bus 202 having m bit lines. The two devices schematically illustrated in FIG. 2, however, may also be realized in software, such as, for example, as different routines running in a processor.
Furthermore, (encrypted) data MT can be transferred from the second device AES via the second bus 204 having m bit lines.
As regards data processing in each of the two devices CPU or AES, the mode of functioning of this processing can be described as follows. The encrypted data of a data stream are received at an input 206 of the first functional block (i.e. of the first device) CPU and decrypted by a decryption key TM (such as, for example, by an exclusive-OR linking or operation or the like). This decryption key TM here may be generated by a one-time pad generator OTPG, however, it may, for example, also be taken from a look-up table. This decryption key TM here corresponds to an encryption key TM used for encrypting the input data stream on the bus 204 from the functional unit AES. In the present case, the encryption key TM and the decryption key TM are identical. As a result of the linking of the encrypted input data with the decryption key in a decrypter 208, plain text data M are output and buffered. For further processing in the functional unit CPU which then is to take place in a masked or encrypted manner, encryption is performed in an encrypter 210 by a T key so that during actual data processing the data are only used in an encrypted/masked form in the functional unit CPU. Subsequently, the processed data are decrypted again by a corresponding T key in a decrypter 212 and encrypted in a subsequent stage (encrypter 214) by another encryption key tm to be able to transfer same again in an encrypted manner when transferring to the second functional block AES via the first bus 202. The further encryption key tm may again be a one-time pad.
The processing in the second functional block AES takes place in analogy, i.e. again decryption is performed by a corresponding decryption key tm which is, for example, also generated by a one-time pad generator OTPG of the further data encryption apparatus, the result being plain text m which is buffered. Again, encryption of the plain text m or the stored version of the plain text m is performed using a T key to execute the actual calculating steps in the functional block AES using the encrypted data.
Subsequently, a value calculated by the functional unit AES is decrypted again, wherein this decrypted value is again produced using the key TM provided by the one-time pad generator OTPG, the result being the encrypted data stream MT transferred to the first functional unit CPU via the second bus 204. The overall circuit diagram is illustrated in FIG. 2, this image showing a combination of encrypted data transfer and encrypted calculation.
The realization illustrated in FIG. 2, however, has several problems. First of all, it is to be noted that the greatest problem is that a plain text portion m and M in such a design results from partitioning the bus lines, in particular using the design rule “registered out”. In particular, an X bus scramble XBS is used for such a partitioning. For such a bus establishing, all automatic tools for establishing a layout try to preferably place, neutral in timing, gates occurring in the center of a bus line. However, a relatively large portion of the line in a bus line can be tapped by this externally (such as, for example, by a probe), which is particularly disadvantageous when transferring plain text on such a bus line in connection with encrypted transfer and encrypted calculation, since such a “plain text line” has to be considered to be the weakest element in a security-relevant data transfer. Only by means of a complicated hand layout can the plain text portion of the bus lines be kept as small as possible.
Furthermore, a temporary key (T key) has to be generated for the encrypted/masked calculation which, however, can only be achieved by additional hardware and/or numerically complicated additional calculations.
Thirdly, it is also to be mentioned that changing the T key is only possible for an “emptied pipeline”, i.e. using a T key on one or several data blocks when calculating in the first functional unit CPU or the second functional unit AES requires applying the key to the respective data block until all corresponding operations have been processed completely.